1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device that has side wall metal layers.
2. Description of the Related Art
Most semiconductor devices used for mobile-communication and satellite-communication are available in the form of high-speed, high-performance small MMICs. The MMIC is composed of active elements such as field effect transistors and bipolar transistors and passive elements such as capacitors and inductors. In such an MMIC, radiation of heat generated from elements and connection to the ground potential are important for the high circuit performance. In the MMIC using a GaAs semiconductor substrate, a metal ground layer is formed on the back surface of the substrate and the elements are formed on the front surface of the substrate.
As disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-5832), a surface pattern is connected to a metal ground layer by side wall metal layers provided on the side walls of a chip or via-holes formed to penetrate the substrate. The metal ground layer functions as a so-called xe2x80x9cplated heat sinkxe2x80x9d (hereinafter, to be referred to as xe2x80x9cPHSfxe2x80x9dto radiate heat generated by the active elements. The via-holes and device-separating trenches can be easily formed in the MMIC using such a GaAs substrate by means of reactive ion etching using a sulfuric acid-based etchant or chlorine-based etchant.
In recent years, researches and development have been conducted to provide electronic devices or light-emitting devices that use nitride-based III-V group compound semiconductor (GaN-based semiconductor) composed mainly of GaN. The GaN-based semiconductor are superior to the conventional GaAs-based field effect transistors in saturation electron mobility and a break-down voltage, and the GaN-based semiconductor would be effective for a high frequency field effect transistor and a high power field effect transistor. Such GaN-based semiconductor is usually grown on a sapphire substrate or a SiC substrate by means of chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).
Conventionally, trenches are formed by a scriber or a dicing saw in the surface of the substrate which is a chemically stable substrate such as a sapphire substrate or a SiC substrate, and the substrate is broken using the trenches, as disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-126923). By this method, the sapphire substrate can be separated into chips, but it is difficult to form metal layers on side walls of the chip.
It may be possible to form a metal ground layer on the surface of the substrate and to carry out mechanical dicing from the back of the substrate such that the metal ground layer is exposed. In this case, however, side walls of the metal ground layer are exposed only. For this reason, there would be a case that the power cannot be stably supplied from the metal ground layer due to dirt or scars in a metal plating process. In such a case, side wall metal layers would fail to have a uniform thickness or a desired shape. As a result, the MMIC cannot provide desired characteristics, and the product yield of the MMIC would be inevitably low.
In conjunction with the above description, a method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-276276). In this reference, a semiconductor substrate is adhered to a support plate. The semiconductor substrate has a source electrode, a drain electrode and a gate electrode through an insulating film in a front surface and an electrode layer at a back surface. The insulating film in a scribe region of the semiconductor substrate is selectively removed and then the semiconductor substrate is selectively etched using the remained insulting film as a mask so that the electrode layer is exposed. A metal layer is formed to connect the source electrode and the electrode layer and the semiconductor substrate is separated.
Also, a microwave monolithic integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-58534). In this reference, a plurality of microwave monolithic integrated circuits are formed on a main surface of a semi-insulative compound substrate. Via-holes are formed between the adjacent integrated circuits to penetrate the substrate. A ground conductor of the integrated circuit is led to a back surface of the substrate through the via-hole. The substrate is separated into the integrated circuits by breaking the semiconductor along the via-holes.
Also, a method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-5880). In this reference, a high frequency, large output FET, a gate electrode (2), a source electrode (3), and a drain electrode (4) are formed on the main surface of a semi-insulative GaAs substrate (1) and covered by an insulating film (5). After the main surface of the semi-insulative GaAs substrate (1) is fixed to a support plate 12 by using wax (13), the substrate is made thin at the back side to have the thickness of several tens of micrometers. Next, a protection film (14) is deposited on the back surface of the thinned substrate. Via-holes (7) are formed using as a mask a protection film pattern (14a) which has been aligned with the source electrode. The protection film pattern is removed and a metal layer (8) is formed on the entire back surface of the substrate and then a heat radiation electrode (9) is formed by a gold (Au) plating method.
Also, a method of manufacturing a compound semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-338522). In this reference, a plurality of circuit elements are formed on a main surface of a semi-insulative substrate. The main surface of the substrate is etched so as to form grooves for separating the substrate into chips. The substrate is adhered to a support plate at the side of main surface. The back surface side of the substrate is grinded until the grooves are exposed. A metal layer is deposited on the entire back surface of the substrate so as to allow the chips to be held. The substrate is peeled from the support plate and the metal layer is cut to dice the substrate into the chips.
Also, a method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-66384). In this reference, an active element is formed on the main surface of a semiconductor substrate. A via-hole opening mask for a ground electrode of the active element and a heat radiation hole opening mask in a region directly below the active element are on the back surface of the substrate such that the via-hole opening mask is larger than the heat radiation hole opening mask in size. The back surface of the substrate is etched using the via-hole opening mask and the heat radiation hole opening mask until the ground electrode of the active element is exposed. At this time, a heat radiation hole does not penetrate the substrate. A metal layer is formed on the back surface of the substrate.
Therefore, an object of the present invention is to provide means for forming side wall metal layers on a semiconductor element made from a substrate that can hardly be processed by chemical reactions, thereby to improve the characteristics of an MMIC and raise the yield thereof.
In an aspect of the present invention, a method of manufacturing a semiconductor device is attained by (a) forming trench sections on a side of one of opposing surface portions of a substrate, wherein at lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate; by (b) fixing the substrate to a support such that the one surface of the substrate fits to the support; by (c) separating a chip from the substrate using the trench sections; by (d) forming a conductive film on side surface portions of the chip and the other surface portion of the chip; and by (e) separating the chip from the support.
Here, the (a) forming step may include cutting the surface portion of the substrate to form the trench sections. In this case, the (c) separating step may be attained by cutting the substrate from the other surface portion of the substrate to the trench section. Alternatively, the (c) separating step may be attained by grinding the other surface portion of the substrate; and by cutting the grinded substrate from the other surface portion to the trench section.
Also, the (a) forming step may be attained by cutting the one surface portion of the substrate to form first trench portions; by forming the power supply metal layer to cover the one surface portion of the substrate and a surface of each of the first trench portions; and by cutting the first trench portions to form second trench sections so that the trench sections are formed. In this case, the (c) separating step may be attained by grinding the other surface portion of the substrate such that the second trench portions are exposed.
Also, the (a) forming step may be attained by forming a peripheral film in a peripheral portion of the chip on the one surface portion of the substrate to form the trench sections. In this case, the (c) separating step may be attained by cutting the substrate from the other surface portion of the substrate to the trench sections. Alternatively, the (c) separating step may be attained by grinding the other surface portion of the substrate; and by cutting the grinded substrate from the other surface portion of the substrate to the trench section.,
Also, the (a) forming step may be attained by forming a peripheral film in a peripheral portion of the chip on the one surface portion of the substrate to form first trench portions; by forming the power supply metal layer to cover the one surface portion of the substrate and a surface of each of the first trench portions; and by cutting the first trench portions to form second trench sections so that the trench sections are formed. In this case, the (c) separating step may be attained by grinding the other surface portion of the substrate such that the second trench portions are exposed.
Also, the (b) fixing step may further include filling a material soluble to a solvent in the trench section.
Also, when the conductive film includes a first conductive film and a second conductive film, the (d) forming step may be attained by (f) forming the first conductive film on side surface portions of the chip and the other surface portion of the chip; and by (g) forming the second conductive film on the first conductive film. In this case, the first conductive film may be formed by a sputtering method or a vapor deposition method, and the second conductive film may be formed by a plating method.